The present invention relates to a high voltage MOS field effect transistor, and more particularly to a high voltage MOS field effect transistor with a channel stopper region for preventing a leakage current between source and drain regions.
It has been known in the art, to which the invention pertains, to provide a channel stopper region around each of the MOS field effect transistors integrated on a semiconductor substrate doped with an impurity at a low concentration. The channel stopper can provide electrical isolation between the individual MOS field effect transistors. The channel stopper comprises a region doped with an impurity of the same conductivity type as an impurity doped in the semiconductor substrate. Namely, the conductivity type of the impurity of the channel stopper is opposite to the conductivity type of the impurity of the source/drain regions. The channel stopper has a higher impurity concentration than an impurity concentration of the semiconductor substrate. The source/drain regions are designed to have a high impurity concentration to reduce resistivity.
If the channel stopper region is formed to be in contact with the source/drain regions, then a p-n junction of the high impurity concentration is formed at the boundary between the channel stopper region and each of the source/drain regions. If the source/drain regions are biased at a high voltage, for example, 20 V, then the p-n junction is biased in a reverse direction at the high voltage. As a result, it is possible that an avalanche break down appears at the p-n junction, namely at the boundary between the channel stopper region and each of the source/drain regions. The avalanche break down causes a leakage current between the channel stopper region and each of the source/drain regions.
In order to prevent the above leakage current, it has been proposed to provide an off-set region between the channel stopper region and each of the source/drain regions. The off-set region is provided to surround the source/drain diffusion regions. The off-set region has a lower impurity concentration than an impurity concentration of the channel stopper region. The impurity of the off-set region is the same conductivity type as the impurity of the channel stopper region. As a result, the off-set region extends under a gate electrode, on which a gate signal is applied. When the gate signal is applied to the gate electrode, then an inversion layer is formed in the off-set region under the gate electrode. This causes a leakage current to flow between the source/drain diffusion regions through the inversion layer in the off-set region under the gate electrode.
In order to settle this problem, it has been proposed to improve the off-set structure under the gate electrode. This improved off-set structure under the gate electrode is disclosed in Japanese laid-open patent application No. 2-15672. FIG. 1 is a plane view illustrative of the MOS field effect transistor with an improved off-set structure under the gate electrode. FIGS. 2A, 2B and 2C are cross sectional elevation views, along A--A, B--B and C--C lines respectively, illustrative of the MOS field effect transistor with an improved off-set structure under the gate electrode. A substrate 21 comprises an n-type silicon substrate. A p-type well region 22 is formed on the n-type silicon substrate 21. Field oxide films 23 are selectively formed on a top surface of the p-type well region 22 to define an active region on the surface of the p-type well region 22. A gate oxide film 24 is selectively formed on the active region of the p-type well region 22. A gate electrode 25 is formed on the gate oxide film 24. Source/drain regions 27-1 and 27-2 of n-type conductivity are formed by implanting an n-type impurity into the surface region of the p-type well region, where the gate electrode 25 and the gate oxide film 24 are used as masks. The n-type source/drain regions 27-1 and 27-2 have a high impurity concentration. In the plane view, a p-type channel stopper region 28 is formed around the active region on which the n-type source/drain regions 27-1 and 27-2 are formed. In the cross sectional elevation view, the p-type channel stopper region 28 is positioned under the field oxide film 23.
At a drain side where the n-type drain region 27-2 is formed, the p-type channel stopper region 28 is provided to surround the off-set region 29 which surrounds the drain region 27-2. The edge of the channel stopper 28 is positioned outside the edge of the field oxide film 23. The drain region 27-2 is applied with a high voltage, for example, 20 V. The off-set region 29 has a low concentration of the p-type impurity. For that reason, it is impossible that the avalanche break down appears at the p-n junction between the drain region 27-2 having a high concentration of the n-type impurity and the off-set region 29 having a low concentration of the p-type impurity. On the other hand, at a source side where the n-type source region 27-1 is formed, there is formed no off-set region. For that reason, the p-type channel stopper region 28 is provided to directly surround the source region 27-1. The edge of the channel stopper 28 is positioned to correspond to the edge of the field oxide film 23. The off-set region 29 beside the drain side is terminated under the gate electrode 25 at an intermediate position where a boundary between the source side and the drain side is positioned. At the source side of the boundary between the source and drain sides, the inner edge of the channel stopper region corresponds to the outer edge of the source region 27-1. At the drain side of the boundary between the source and drain sides, the inner edge of the channel stopper region extends to be in contact with the outer edge of the drain region 27-2. The above structure allows a high voltage of 20 V to be applied to the drain region 27-2, and the source region to be grounded, so that the source and drain regions are biased with a high voltage.
The above structure has a problem as described below. Under the gate electrode at the drain side of the boundary, the off-set region 28 resides. At this position, it is possible that the leakage current appears. In the above structure, there still remains the problem with the leakage current.
According to the above structure, the drain region 27-2 resides in the vicinity of the gate electrode 25. If the drain region 27-2 is applied with a high voltage such as 20 V, an excess high electric field is generated between the gate electrode 25 and the drain region 27-2. To operate this transistor under the high bias voltage such as 20 V, it is necessary to relax the excess high electric field. For this purpose, it is possible to further provide a lightly doped region surrounding the drain region 27-2 wherein the lightly doped region has a lower impurity concentration than the impurity concentration of the drain region. The lightly doped region has the same conductivity type as the drain region. Providing the lightly doped region along its side abutting the channel region makes the drain region 27-2 apart from the gate electrode. A distance between the drain region 27-2 and the gate electrode 25 is enlarged. As a result, the intensity of the electric field between the drain region 27-2 and the gate electrode 25 is reduced, while the level of the voltage applied between those. This structure simultaneously causes another problem with increase in the ON-resistance of the transistor.
When the transistor turns ON, the current flows between the source/drain regions via the channel region. If the lightly doped region is provided along its side abutting of the channel region, the current flows via the lightly doped region. As described above, the lightly doped region has a low impurity concentration. Thus, the lightly doped region has a higher resistivity than the resistivity of the source/drain regions. As a result, the effective ON-resistance between the source and drain regions is increased by providing the lightly doped region.
Under the above circumstances, it has been sought to develop a novel structure of the channel stopper under the gate electrode for the high voltage MOS field effect transistor.